This manual relates to the MOS 6500/1. The 6500 was not produced in quantity because it was too close to the Motorola 6800. Chuck Peddle quickly redesigned the chip into the fabled 1Mhz MOS / CSG 6502 (and several derivatives like the 6509) which ran almost all Commodore equipment from 1978 to the mid 1980’s. General information on all of the 650x line is available in our History tab.
“The 6500/1 is a complete high performance 8-bit NMOS microcomputer on a single chip and is totally upward / downward software compatible with all members of the 6500 family.
The 6500 /1 consists of a 6502 CPU, and internal clock oscillator, 2048 bytes of Read Only Memory (ROM), 64 bytes of Random Access Memory (RAM) and flexible interface circuitry. The interface circuitry includes a 16-bit programmable counter / latch with four operating modes, 32 bidirectional input / output lines (including two edge-sensitive lines). five interrupts and a counter I/O line.”
The graphics below were converted from a large .PDF on Richard Cini’s excellent site which is now defunct but can still be accessed on Archive.org HERE. It was reproduced October 17, 2002 with permission granted in July of 2002. Thanx again Richard!
