PLUS/4 User port

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VANEPS
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PLUS/4 User port

Post by VANEPS »

Does anyone have information on Commodore plus/4 user port programming maybe with a short example. I am familiar with the Vic 20 and 64 user port programming but the plus 4 has different address locations that I am unfamiliar with. Thanks in advance for any help.
Minion
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Re: PLUS/4 User port

Post by Minion »

VANEPS wrote:Does anyone have information on Commodore plus/4 user port programming maybe with a short example. I am familiar with the Vic 20 and 64 user port programming but the plus 4 has different address locations that I am unfamiliar with. Thanks in advance for any help.
An example would be helpful for me too. Plus 4 is making things confusing.
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LoneWolf33
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Re: PLUS/4 User port

Post by LoneWolf33 »

Yesterday evening I've dug out my old Plus/4 and a wiring diagram for it.
The user port is shared between a hardware serial port (unlike the C64 which has software emulated one),
and an 8 bit parallel port. The serial section (capable to 19.2 kbps) is well documented, so I think I can't add
anything interesting to it. The parallel port is implemented with an 6529B Single Port Interface (SPI) IC.
It has 20 pins, 8 pins are facing towards the data bus, another 8 pins towards the user port
in the following order:
P0 -> User Port pin B
P1 -> User Port pin K
P2 -> User Port pin 4
P3 -> User Port pin 5
P4 -> User Port pin 6
P5 -> User Port pin 7
P6 -> User Port pin J
P7 -> User Port pin F

The remaining pins of the 6529B are Chip Select (CS) and R/W (and 2 power supply pins). CS is connected to the 7700PLA,
while the R/W is connected to the CPU R/W pin. This chip does not supports independent data directions on the port lines,
all 8 port pins/lines are operating as input or output (no data direction register either). Data direction is determined by the
state of CS and R/W pins. Low CS and R/W means output mode, while low CS and high R/W means input mode.
When the Plus/4 is turned on (mine after sitting 10+ years) the 6526B appears to be in output mode, all data lines are
set to high state. The data port is mapped to $FD10 (64784 decimal) memory address. You can enable or disable
the port lines by poking values to this address. I've checked the port line voltages with a multimeter and it seem to be working.
Last edited by LoneWolf33 on Fri Mar 04, 2016 4:39 pm, edited 1 time in total.
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LoneWolf33
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Re: PLUS/4 User port

Post by LoneWolf33 »

Update:
Although the 6529B IC is capable to read from the port,
it seems this mode is not implemented in the Plus/4.
Only the write/output mode works.
I've opened up my Plus/4 to check the CS and R/W lines of the port IC:
Plus4_opened_up.JPG
Plus4_opened_up.JPG (127.89 KiB) Viewed 6399 times
The 7700 PLA enables the 6529B port IC by lowering the it's CS line
for a few microsenconds in every 20 milliseconds. When the 6529B IC is
enabled the R/W line is always held high by the CPU, which results output mode.
6529B.JPG
6529B.JPG (118.98 KiB) Viewed 6399 times
Red: CS line
Blue: R/W line

Read operation would require low state of both R/W and CS lines.

So as far as I can tell the parallel section of the Plus/4 User Port
is limited to output mode.
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